| 摘要 |
PROBLEM TO BE SOLVED: To achieve a shift register that normally operates even when the amplitude of a clock signal is small, and at the same time has less power consumption. SOLUTION: For each SR flip-flop F1 for composing a shift register 11, a level shifter 13 for boosting a clock signal CK is provided, thus the transmission distance of the boosted clock signal and the load capacity of the level shifter 13 are reduced as compared with a case where the clock signal is boosted by only one level shifter for transmitting to each flip-flop. Each level shifter 13 operates while the level shifter 13 at the previous stage outputs a pulse, and stops the operation when the pulse output is completed, thus each level shifter 13 operates only when the clock signal CK is required to be supplied to the corresponding SR flip-flop F1, and as a result the power consumption of the shift register that normally operates even when the amplitude of the clock signal is small can be reduced. |
