DEVICE AND METHOD FOR DIGITAL SIGNAL PROCESSING

摘要

PROBLEM TO BE SOLVED: To decrease the number of gates by supplying a total stored in a 1st register as an input and storing the stored total in a 2nd register in response to the reciprocal number of a clock signal so that two results are summed up in one clock cycle. SOLUTION: The total stored in the 1st register is supplied as the input and the stored total is stored in the 2nd register in response to the reciprocal number of the clock signal so that the two results are summed up in one clock cycle. An adder 510 receives a 1st input from a multiplier 520 and its 2nd input is supplied from the 1st register FF1 530. The register FF1 530 stores the result of the adder 510 and the 2nd register FF2 531 stores the output of the register FF1 530. The registers 530 and 531 are clocked with a clock signal, which is inverted to double the production rate without doubling the clock by the register FF2 531.