LOW POWER CONSUMPTION DIGITAL LOGIC CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a logic circuit that facilitates timing design of a clock system and reduces the design period in the logic circuit of a gated clock system. SOLUTION: The logic circuit that is provided with a gate circuit 2 that passes or masks a received clock signal depending on a value of a clock enable signal and where an output of a gate circuit 2 is given to a clock input terminal used to control latch timing of a latch circuit 1 receiving data, is provided with a selector 3 that receives input data DATA (1) and output DATA (0) of the latch circuit 1 and outputs either of them by using an enable signal for a selection signal, and the output of the selector 3 is connected to a data input terminal D of the latch circuit 1.