| 摘要 |
<p>PROBLEM TO BE SOLVED: To eliminate impression of unnecessary word line voltage to shorten the read time by providing a recognizing means for determining whether an input address signal designates the upper order bits of data or lower order bits of data. SOLUTION: A semiconductor memory device includes multi-level type memory cell transistors ML0, ML1, MR0, MR1 for storing the information of a plurality of bits. Word line voltages of a plurality of levels are previously specified to read a plurality of bits. An address recognizing circuit 1 determines whether the address signal designated upper order bits of data or lower order bits of data. A row decoder 2 selects the word line depending on the address signal and applies only the minimum word line voltage required for read of the upper order bits of data or lower order bits of data among the word line voltages of a plurality of levels depending on the result of the address recognizing circuit 1.</p> |
