| 摘要 |
PROBLEM TO BE SOLVED: To fetch display data in a drain driver in a low clock frequency with an interface not adopting an LVDS system. SOLUTION: This device is equipped with a clock multiplying circuit PLL for multiplying by (a) the frequency of a clock signal CL inputted from a computer to an interface circuit, and with a parallel-serial conversion circuit for converting the number of display data to the number of (n) transferred from the computer into (m). The display data to the number of (m) is fetched in a drain driver with a double edge of a clock a×CL, in the relation between (m) and (n), expressed as m<=n, and n/m=1/a ((a) is an integer).
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