| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock signal generating circuit that generates a clock signal with a desired frequency even when an oscillation circuit with comparatively low frequency accuracy is employed and to provide a clock frequency adjustment method. SOLUTION: Each of frequency division data from a memory storing a plurality of frequency division data is sequentially and repetitively read and every time the frequency division data to be read are coincident with the number of pulses of a constant frequency signal generated from an oscillation circuit 2, a signal with an inverted logic level is outputted as a clock signal. In the case that the frequency of the constant frequency signal is lower than a desired request frequency, at least a value of the frequency division data stored in a memory 35 is decreased and in the case that frequency of the constant frequency signal is higher, at least a value of the frequency division data stored in the memory 35 is increased through the adjustment.
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