| 摘要 |
PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device, having a fine Cu wiring which is low in wiring resistance and suppressed in defects, such as peel-offs or air gaps by a single or dual damascene process. SOLUTION: (a) A hole 103 and a groove 104 are made in an interlayer insulating layer 102 on a lower wiring 101 to form an electrode and an upper wiring. (b) A barrier metal layer 105 is deposited on a side and bottom of the hole 103 and the groove 104. (c) A Ta layer 106 is deposited only on the part of the groove 104 in the vicinity of a surface of a substrate and on the substrate surface 110. (d) A Cu seed layer 107 is selectively formed on the bottoms of the hole 103 and groove 104, and a Cu layer 108 is deposited with use of the seed layer 107 as a seed through plating. (e) Finally excess parts are removed by a chemical mechanical polishing(CMP) process to form a Cu electrode 103A and a Cu upper wiring 104A.
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