| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM refresh control circuit which reduces a power consumption in the refresh operation of a DRAM. SOLUTION: In this DRAM refresh control circuit 1, a refresh request from a refresh timer 2 is mediated with an access operation by a CPU by using a conflict control circuit 3 so as to be given to a refresh address counter 6 and a RAS generation circuit 5, and the refresh address counter 6 outputs a refresh address to a file control memory 10. The file control memory 10 stores a significant-information existence bit which indicates the existence of significant information in every row of a DRAM 11, and the significant-information existence bit of an address corresponding to a row to be refreshed is output to the RAS generation circuit 5. The RAS generation circuit 5 outputs a RAS signal to the DRAM 11 when the significant-information existence bit is input, and it refreshes a row, to be refreshed, in the DRAM 11. When the significant- information existence bit is not input, the RAS generation circuit 5 does not generate a RAS signal, it does not refresh the DRAM 11, and the power consumption of the DRAM refresh control circuit 1 is suppressed.
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