发明名称 CONVOLUTION ARITHMETIC UNIT
摘要 PROBLEM TO BE SOLVED: To decrease delays between an input signal and an output signal by dividing an impulse response into nonequivalent blocks and performing convolution arithmetic using FFT. SOLUTION: In the case of processing an impulse response, the data of the impulse response are inputted to an impulse response buffer, in the order (11) to obtain N samples as data divided into pieces. Every block is subjected to FFT processing, and FFT processing result are stored in the impulse response buffer (14). In the case of processing an input signal, the input signal is inputted to respective input buffers successively for every N/16 sample (15), every block is subjected to FFT processing are performed, and processing results are stored in a buffer for the input signal (18). Then the FFT processing results of the input signal for every block and the FFT processing results of the impulse response are multiplied (19), inverse FFT processing for the multiplication result for every block are performed (20), and the multiplication results are added by seven blocks (21). The addition results are written sequentially to an output buffer as a convolutional arithmetic result of the N samples (22).
申请公布号 JP2000341139(A) 申请公布日期 2000.12.08
申请号 JP19990152204 申请日期 1999.05.31
申请人 VICTOR CO OF JAPAN LTD 发明人 SUZUKI TAKUMA
分类号 G10K15/12;H03M13/23 主分类号 G10K15/12
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