| 摘要 |
PROBLEM TO BE SOLVED: To design a processing module by taking into consideration a delay time in order to reduce influences due to signal delay caused by a resistance and a capacity element that a data bus has when a signal line of the data bus or the like becomes long. SOLUTION: An interface circuit 13 is provided in a bus and the transmission of a signal is controlled. Regarding data and the like to be transmitted from a central processing unit, they are not delayed in the interface circuit but a signal is given to an extended bus as it is. Regarding a data signal or the like to be transmitted to the central processing unit, it is delayed for a specified time at a latch 25 of the interface circuit and transmitted to the central processing unit. Since only the data signal to the central processing unit is latched, it is possible to suppress a circuit scale of the interface.
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