| 摘要 |
<p>A method for selecting which covers to retain for each node reduces the computational burden for large logic cones and large cell libraries. At each node only K covers are retained. These covers have timing preformances which are centered around the ideal timing performance for that node, and do not include inferior covers. The computational burden in selecting the covers for each node is based on the number K, and the number of inputs to that node.</p> |
