| 摘要 |
An Asynchronous Transfer Mode (ATM) cell architecture overcomes the inability of a Universal Test and Operations PHY Interface for ATM Level 2 (UTOPIA L2) standard to service more than a limited number of ports and conduct cell transfers across a backplane. The invention provides both ATM-PHY layer (41) and PHY-ATM layer transport capability. The ATM layer is part of an ATM layer-containing circuit card, including a master multiple ATM layer (45), multiple Phy layer (MAMP) backplane interface unit (55), that provides ATM cell connectivity between a first UTOPIA L2 based bus (43) and the backplane. Each PHY layer-containing port card (50) includes a second UTOPIA L2 based bus coupled to multiple PHY ports, the number of which is less than the total PHY port capacity of the first UTOPIA L2 based bus.
|
