Dynamic random access memory (DRAM) cells arrangement, each cell having one vertical transistor and one capacitor

摘要

A DRAM-cell arrangement includes memory cells each comprised of a capacitor and a transistor, the latter being a vertical structure transistor. A memory node (SK) of the capacitor is in a first well/recess (V1) in a substrate (1), with the capacitor dielectric (KD) between the memory node (SK) and the substrate (1). The memory node (SK) borders on the substrate (1) at least in a contact zone of a lateral surface of the first well or recess (V1). A second well or recess (V2) of the substrate (1) is spaced from the first well or recess (V1), and a transistor gate electrode is arranged in the second well (V2) at least at a first lateral surface of the second well (V2), and is isolated from the substrate (1) by a gate dielectric (GD), which at least borders on the first lateral surface. Upper (S/DO) and lower (S/DU) source/drain zones of the transistor are provided in the substrate, the upper (S/DO) source/drain zone bordering on the memory node (SK) at the second well (V2) and in the contact zone of the side surface of the first well or recess (V1). The lower source/drain zone (S/DU) is arranged deeper in the substrate than the upper source/drain zone (S/DO) and borders on the second well or recess (V2).