| 摘要 |
PROBLEM TO BE SOLVED: To provide a logic simulation device which reduces a memory quantity to be used and a simulation time in the case of simulating the entire LSI circuit being a simulation object. SOLUTION: This logic simulation device provided with a means which inputs layout result information, extracts the connection relation of cells, cell delay, a timing value and a wire delay value between leaf cells and generates a simulation load model is provided with a means 101 which divides the connection relation of the leaf cells into groups in the input-output unit of a flip-flop, generates a logic model in each of the groups, calculates optimum simplification logic due to the comparison with the logical expression of a logic database and replaces the connection relation between flip-flops composed of a plurality of cells with one single simplified cell, a means 102 which changes delay and timing values in accordance with the connection relation between simplified input and output and a means 103 which generates a simplified simulation load mode from the connection relation between the simplified input and output and changed delay and timing information.
|
