摘要 |
In the present invention, inside a large scale integrated circuit (LSI) chip, the on-chip capacitor (18) to suppress a ground-bounce is arranged in a region (14) below a first wiring group (24) as well as between adjacent two wirings (10, 11) of a second wiring group (23). Alternatively, the on-chip capacitor (18) is arranged in a region (21) obtained by combining the foregoing region (14) with a region (20) where the function block (17) cannot be arranged. <IMAGE> |