发明名称 |
Biasing stage for biasing the drain terminal of a nonvolatile memory cell during the read phase |
摘要 |
<p>The read circuit (50) comprises a biasing stage (12) connected to the memory cell (6) to be read and having the purpose of biasing the drain terminal of the memory cell (6) at a preset operating potential, typically 1 V; and a regulating circuit (52) connected to a supply line (2) set at a supply voltage (VCC) and supplying to the biasing stage (12) a bias current (Ip) which is stable as the temperature and the supply voltage (VCC) vary. <IMAGE></p> |
申请公布号 |
EP1058270(A1) |
申请公布日期 |
2000.12.06 |
申请号 |
EP19990830348 |
申请日期 |
1999.06.04 |
申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
MICHELONI, RINO |
分类号 |
G11C16/06;G11C11/56;G11C16/02;G11C16/24;(IPC1-7):G11C16/06 |
主分类号 |
G11C16/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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