CIRCUIT FOR COMPENSATING DATA RETENTION VOLTAGE OF SRAM

摘要

PURPOSE: A data retention voltage compensating circuit is provided to increase the level of the supply power voltage applied to cells by detecting a lowered supply power voltage if a chip enters a retention mode. CONSTITUTION: A data retention voltage compensating circuit includes a booster(20) for boosting the level of the supply power voltage(Vcc) applied to chips based on a chip driving signal(CE). A supply power voltage detector(30) detects the supply power voltage(Vcc) applied to the chips to output a low voltage detection signal(LVCCDET). The first transfer gate(TG21) has a main terminal for receiving the output of the supply power voltage(Vcc) and a sub terminal for receiving the output of the supply power voltage(Vcc) via an inverter(INV21). The first transfer gate(TG21) shuts or transfers the output(VPP) of the booster(30) to supply it to a static RAM cell. The second transfer gate(TG22) has a main terminal for receiving the output of the supply power voltage detector(30) and a sub terminal for receiving the output of the supply power voltage detector(30) via the inverter(INV21). The second transfer gate(TG22) transfers the supply power voltage(Vcc) to supply or shut it to the static RAM cell.