| 摘要 |
PURPOSE: A clock phase comparator is provided to reduce time required to synchronize two signals by delaying a reference signal for a determined time and outputting the state of the target signal at the rise edge of the delayed reference signal. CONSTITUTION: A first clock phase detector(10) receives clock input signal and clock return signal and outputs the speed difference of the two clock input signals. A delayer(20) delays the clock input signals by 90 degrees. A second clock phase detector(30) receives the delayed clock input signal and the clock return signal delayed by the delayer(20) and detects if there is a 90 degrees of phase difference. The second clock phase detector(30) outputs the detection signal to a delay synchronization loop circuit.
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