| 摘要 |
PROBLEM TO BE SOLVED: To greatly lengthen record length without sacrificing the other characteristics of the fetch process of an input signal. SOLUTION: This structure is provided with a plurality of arrangements (arrangement A, B) of memory cells, a bus for input signals to be tested (line for analog signal) connected in parallel to each of the plurality of fetch cells. Each of the plurality of arrangements have a plurality of memory cells 16 arranged in a matrix state. Each of memory cells is enabled depending on the combination of a row signal and a column signal. A column 1A of a memory cell of one arrangement out of the plurality of arrangements relates to a column 1B of a memory cell of the other arrangement out of the plurality of arrangements, and related columns receive commonly an output from one of a plurality of the fetch cells 10. A memory cell 16 to be activated is selected by a plurality of signals (1A to NA, input enable A, output enable A, GE1). |
