BUS LOCK CONTROLLER

摘要

PROBLEM TO BE SOLVED: To reduce the possibility of temporary lowering of performance even when an error is generated by using mechanism to control a bus lock signal and mechanism to release the signal by an instruction to be executed by a processor. SOLUTION: A transfer error signal BERR passes a bus control circuit 102 and is inputted in a processor 101 as a machine check interruption signal MCINT for the processor 101. Bus lock signals BLOCK and LOCK are immediately negated by directly making access to a bus lock releasing circuit 104 by the processor 101. The bus lock signals BLOCK and LOCK are negated by such operation by the bus control circuit 102 by which a bus lock releasing signal LCLR is received from the bus lock releasing circuit 104. As a result, the bus lock signal is immediately released and a bus is immediately used by other processor modules. Therefore, the possibility of the temporary lowering of the performance of a communication computer is reduced.