| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of signal terminals by using a signal terminal exclusively for setting test mode also as an actually operating terminal in a semiconductor integrated circuit incorporating an oscillation stabilization wait circuit. SOLUTION: In this test mode setting method, an oscillation clock is inputted from a fourth terminal, a rest signal releasing a reset condition is inputted from a third terminal, data for setting test mode is inputted from a plurality of second terminals when a gate pulse by several clocks is generated after reset is released, the transition of data is detected as an edge, a test mode setting data latch permission signal 10 is generated when it coincides with a test mode recognition key setting register 8 set as an initial value, and test mode setting data inputted from a plurality of first terminals is decoded to generate test mode and is held in a latch circuit 12 by the test mode setting data latch permission signal 10 to set test mode specified in a semiconductor integrated circuit.
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