发明名称 DEVICE FOR PHASE DECIDING AND ADJUSTING BETWEEN DATA CLOCKS
摘要 PROBLEM TO BE SOLVED: To eliminate the need for phase adjustment by line maintenance personnel, to reduce circuit scale and to reduce cost for a device. SOLUTION: This device 102 includes a delay circuit 114 that delays data from a terminal, a flip-flop circuit (FF) 118 that captures the data from the terminal with a prescribed timing of a clock of a clock oscillation circuit, a flip-flop circuit 120 that captures the data from the circuit 114 in a prescribed timing, a flip-flop circuit 122 that captures data in a prescribed timing of a clock from an inverter 116, a flip-flop circuit 124 that captures data from the circuit 114 in a prescribed timing of the clock from the inverter 116, and a decision/selection circuit 134. The circuit 134 includes a set/reset circuit 130 and a selector circuit 132, that selects data (a) or (b) in response to a signal 150.
申请公布号 JP2000332734(A) 申请公布日期 2000.11.30
申请号 JP19990139868 申请日期 1999.05.20
申请人 OKI COMTEC LTD 发明人 HAYAKAWA HIDEAKI
分类号 H04L7/00;H04L7/02 主分类号 H04L7/00
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