STANDARD CELL, AND SEMICONDUCTOR INTEGRATED DEVICE AND ITS LAYOUT DESIGNING METHOD

摘要

PROBLEM TO BE SOLVED: To control the threshold voltage of a transistor(TR) in a cell when the layout of a semiconductor integrated circuit is designed by a standard cell system. SOLUTION: A pin 23 for an N well area which is not electrically connected to a power line 15 supplying a 1st source potential to the source area of a P channel TR is provided, so a potential different from the source area of the P channel TR can be supplied to the N well area 19 and the threshold voltage can be controlled. Further, a pin 24 for a P well area which is not electrically connected to a ground line 16 supplying a 2nd source potential (ground potential) to the source area of an N channel TR is provided, so a potential different from the source area of the N channel TR can be supplied to the P well area 20 and the threshold voltage can be controlled.