WIRING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To enable highly accurate improvement of wiring delay by securing a delay adjustment cell arranging area on the lower side of a net to violate delay restriction and as piling on the lower side of power source wiring and ground wiring to be provided in a wiring area. SOLUTION: Delay time due to wiring is calculated for all signal nets decided by an approximate wiring route. The calculated delay time calculated by every signal net is compared with delay restriction time preset by every signal net and a signal net in which the calculated delay time exceeds the delay restriction time is extracted. A delayed value is improved for a signal net to violate the delay restriction by enhancing a driving ability of a transistor connected with an output terminal to constitute each net. A slot array 30 in which a slot 30a corresponding to the delay adjustment cell as the delay adjustment cell arranging area in which the delay adjustment cell to adjust the delay time of the net to violate the delay restriction can be inserted is arranged is secured as piling on the lower side of the net to violate the delay restriction of the wiring area and lower side of the power source wiring 31 and the ground wiring 32.