| 摘要 |
PROBLEM TO BE SOLVED: To reduce via resistance, improve the electromigration resistance, and decrease the wiring capacitance between adjacent upper-layer wires even if a groove for upper-layer wiring and a via hole pattern are misaligned when formed at the same time. SOLUTION: This semiconductor device has a wiring structure constituted by forming via holes 7a to 7d in a 1st inter-layer insulating film covering lower- layer wires 3a to 3d, a 2nd inter-layer insulating film on the 1st inter-layer insulating film across an etching stopper film 8, grooves 10a to 10d for upper- layer wiring in the inter-layer insulating film, and via contacts 11a to 11d and upper-layer wires 12a to 12d in the via holes 7a to 7d and upper-layer wiring grooves 10a to 10d. The etching stop film is absent on the 1st inter-layer insulating film between the adjacent upper-layer wires 12a to 12d.
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