发明名称 RANDOM LOGIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To save the electric power in sleep mode by turning off the power source of a specific circuit in sleep mode and providing a sub-threshold leakage current preventing means between a front-stage and a rear-stage latch. SOLUTION: The front-stage latch part and rear-stage latch part of a flip-flop circuit are separated by a transfer gate 50, which is controlled with a control signal TG2 generated in synchronism with a basic clock and its inverted signal TG2B. In sleep mode, the electric power VCCO supplied to an input part, the front-stage latch part, and an output part is turned off to hold data by the rear-stage latch part, and voltages which are lower and higher than the VSS level are generated by level converting circuits 59 and 60 to apply a negative potential to the respective gates of the transfer gate 50. Leak currents of respective transistors are prevented and the data can be held by the rear-stage latch part to prevent a leakage current flowing to the front-stage latch part in a power-off state.
申请公布号 JP2000332598(A) 申请公布日期 2000.11.30
申请号 JP19990135088 申请日期 1999.05.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 OISHI TSUKASA;HIDAKA HIDETO
分类号 H03K19/20;H03K3/012;H03K3/356;H03K3/3562;H03K19/0944;(IPC1-7):H03K19/20;H03K19/094 主分类号 H03K19/20
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