| 摘要 |
A master circuit and a slave circuit are provided. The master circuit has a first presettable counter for setting a first cycle, and a clock pulse generating circuit for producing an instruction pulse at the first cycle determined by the first presettable counter, the slave circuit has a second presettable counter for setting a second cycle, and a pulse generating circuit for producing a plurality of pulses at the second cycle in response to the instruction pulse from the master circuit. There is provided a gate array comprising a plurality of gates and formed into an integrated circuit having a plurality of pins, and provided for relaying signals among signals from the master circuit and slave circuit. A transistor array is connected to an input for decreasing an input impedance of the controller. <IMAGE> |
