发明名称 VIA FORMING METHOD FOR MULTILAYER PRINTED BOARD
摘要 PROBLEM TO BE SOLVED: To obtain the forming method of a via of a multilayer printed substrate, having a high aspect ratio with which the surface side conductive pattern of a surface side substrate and the conductive pattern of a core substrate are electrically connected, on which a high density via is formed. SOLUTION: A prepreg surface side substrate 30 is provided on the surface of a core substrate 20, consisting of printed substrates 21 and 22 having conductive patterns 25, 26 and 27 which are conductive to the front and the back sides via vias 23 and 24. A via hole 33, having an aspect ratio of 1 or larger from the surface of the surface side substrate 30 to the conductive pattern 25 on the surface of the core substrate 20, a metal layer 34 is deposited on the surface of the conductive pattern 25 in the via hole 33 through electrolytic plating, using the conductive pattern 27 on the backside of the core substrate 20 or a conductor which conducts to the conductive pattern 27 as an electrode, and a conductive path 35, which is conductive to the conductive pattern 25, is formed on the surface side in the via hole 33 by electroless plating and electrolytic plating via the metal layer 34.
申请公布号 JP2000332417(A) 申请公布日期 2000.11.30
申请号 JP19990137450 申请日期 1999.05.18
申请人 SUMITOMO METAL ELECTRONICS DEVICES INC 发明人 AKAHO KAZUNORI
分类号 H05K3/46;(IPC1-7):H05K3/46 主分类号 H05K3/46
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