| 摘要 |
<p>A path memory and likelihood update circuit 16 provided in a two-step SOVA decoder includes eight RAMs 32a, 32b, ..., 32h to store path selection information indicative of a selection of a most likely path in each state of an input convolutional code, a trace result memory circuit 34 to store the result of most likely path tracing and output it as delay trace result signal s42, a most likely path DELTA memory circuit 35 to select and store a metric difference for the most likely path based on the delay trace result signal s42 and output it as delay most likely DELTA signal s43, and a minimum DELTA memory circuits 37a and 37b to store a minimum value of the metric difference for the most likely path in each state of the convolutional code based on the delay trace result signal s42 and delay most likely DELTA signal s43. <IMAGE></p> |
