Method of symmetrically implanted punch-through stopper for a rugged DMOS power device

摘要

A structural enhancement to a conventional DMOS process flow addresses the well-known destructive latch up problem. The additional steps include a symmetric "deep" punch-through stopper implant and additional thermal budget to remove silicon damage and distribute the ionized dopants appropriately. The purpose of the implant is to create a low resistance base region within the parasitic bipolar transistor to prevent the device from activating under high current conditions. In terms of circuit characteristics, the goal is to lower the voltage drop at node Vx in FIG. 1C during avalanche breakdown. This structure also provides a means of suppressing the phenomena of punch-through breakdown which can also lower the device's voltage reading.