| 摘要 |
An inter-processor communication system for a multi-processor environment wherein each processor has an associated processor system controller comprising an inter-processor communication registers (IPC Comm Reg). The IPC Comm Reg further comprising a response command register (CMD1 Reg), a non-response command register (CMD2 Reg), and a response register (RSP Reg). During inter-processor communication, the IPC Comm Reg of an initiating processor is coupled to the IPC Comm Reg of a target processor via the IPC bus so that data can be transmitted and one or more of a set of control flags of the target IPC Comm Reg is cleared or set in response to a write or read operation. In the inter-processor communication method for communication between multiple processors the initiating processor system controller coupled to an initiating processor detects the state of a set of status control flags of an initiating IPC Comm Reg associated with that initiating processor. In response to the detected state of the set of status control flags, the initiating system controller writes data to a remote target IPC Comm Reg of a remote target processor system controller, and also sets an associated interrupt flag in the target IPC Comm Reg in response to that write operation. The target system controller then detects the set interrupt flag in the target IPC Comm Reg, and in response thereto, reads data from the target IPC Comm Reg. Moreover, the initiating and/or target system controller may perform additional command sequence depending on the communication mode selected, i.e., auto-response method, CPU-response method, or non-response method.
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