发明名称 |
Instruction to normalize redundantly encoded floating point numbers |
摘要 |
The present invention is an apparatus to normalize a floating point number. The apparatus has a first storage area comprising the floating point number. The floating point number comprises an exponent field and an explicit bit. The apparatus further comprises a circuit to normalize the floating point number when the explicit bit is not set and the exponent field has a first predetermined value identifying a redundant denormal encoding of the floating point number. Otherwise the encoding of the number is not changed by the circuit.
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申请公布号 |
US6154760(A) |
申请公布日期 |
2000.11.28 |
申请号 |
US19950562899 |
申请日期 |
1995.11.27 |
申请人 |
INTEL CORPORATION |
发明人 |
SHARANGPANI, HARSHVARDHAN |
分类号 |
G06F5/01;(IPC1-7):G06F7/00;G06F7/38 |
主分类号 |
G06F5/01 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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