发明名称 |
Delay locked loop device of the semiconductor circuit |
摘要 |
Delay Locked Loop device generates an internal clock by receiving an external clock. Multiplexer is provided to receive N delay signals outputted from the first to Nth delay elements which receives the external clock. The Delay Locked Loop device generates the internal clock by selecting one of the N delay signals. The phase of the internal clock follows the phase of the external clock.
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申请公布号 |
US6154073(A) |
申请公布日期 |
2000.11.28 |
申请号 |
US19980196121 |
申请日期 |
1998.11.20 |
申请人 |
HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. |
发明人 |
CHOI, JAE MYOUNG |
分类号 |
G06F1/10;G06F1/12;G11C11/407;H03K5/13;H03L7/081;H03L7/089;(IPC1-7):H03L7/00 |
主分类号 |
G06F1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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