发明名称 POWER-DOWN CIRCUIT
摘要 A power-down circuit includes a power-on reset circuit that determines whether the supplied power falls below a prescribed level and, in response, outputs a reset signal for at least a prescribed period of time. A power supply latching circuit is responsive to the power-on reset circuit for switching on a power supply switching circuit to supply power from a power supply when the reset signal is not output. A power-down shutdown circuit, preferably under software control, and a power cutoff circuit, may be coupled to the power supply latching circuit, or alternatively the power-on reset circuit, for shutting down the power supplied from the power supply.
申请公布号 CA2243895(C) 申请公布日期 2000.11.28
申请号 CA19982243895 申请日期 1998.07.27
申请人 PITNEY BOWES INC. 发明人 NACLERIO, EDWARD J.;CHEN, WEI C.;SCHOONMAKER, RICHARD P.;DEGROOT-THOMAS, JOHANNA
分类号 G06F1/24;G06F1/30;(IPC1-7):G06F1/30 主分类号 G06F1/24
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