Semiconductor device with improved planarity and reduced parasitic capacitance

摘要

In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without increasing manufacturing steps in number. A semiconductor substrate is provided at its main surface with an isolation region formed by a trench, and a dummy region leaving the main surface is formed in the isolation region for the purpose of reducing an influence by the difference in level in a later step. The dummy region includes p- and n-type impurity regions each extending a predetermined depth from the surface. Since a pn junction occurs at the bottom of the impurity region, a depletion layer spreads in the pn junction, and thereby reduces a parasitic capacity between the dummy region and a conductive interconnection located in a crossing direction at a higher position. The impurity regions and source/drain regions of p- and n-channel transistors in active regions are simultaneously formed by impurity implantation.