| 摘要 |
A method of fabricating buried bit line flash EEROM with shallow trench floating gate for suppressing the short channel effect is disclosed. The method comprises following steps. Firstly, a pad oxide layer and a conductive impurity (such as phosphorus) doped polysilicon layer is successively formed on the silicon substrate. Then, an oxidation process is performed to oxidize the polysilicon layer and to drive in the conductive impurities. After coating a patterned mask on the resultant surface to define a plurality of buried bit line regions, a dry etch is used to etch away the unmask regions till the silicon substrate is slightly recessed to form shallow trenches. Subsequently, the photoresist is stripped, and a gate dielectric layer, such as gate nitride or oxynitride layer is formed on the resultant surface. After refilling a plurality of trenches with a conductive impurity doped silicon layer, a planarization process such as CMP is followed to form a plain surface using the gate dielectric layer as an etching stopped layer. A stacked ONO layer is then deposited as an interpoly dielectric layer; and finally another a conductive impurity doped polysilicon layer is formed and patterned to be as word lines.
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