| 摘要 |
In a semiconductor memory device, charge transfer gates and a bit line precharging/equalizing circuit are inserted in the order mentioned in a bit line pair between memory cells and a sense amplifier. When the transfer gates are off, data of the memory cells are read out to the bit line pair located on the memory cell side. Subsequently, when the transfer gates are turned on, the data are transferred to the bit line pair located on the sense amplifier side. Thereafter, the transfer gates are turned off on the basis of a threshold value of the transfer gates. Then, the memory cell data transferred to the sense amplifier side are amplified by a conventional DRAM method. The bit line precharging/equalizing circuit does not require a large area. It is therefore possible to miniaturize the semiconductor memory device.
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