| 摘要 |
PURPOSE: A logic circuit and a logical unit are provided to prevent non-adiabatic loss by constituting logic function circuit or reversible logical computation unit by NMOS transistor only and compensating swing reduction caused by the NMOS transistor using a pair of PMOS transistors. CONSTITUTION: A logic circuit comprises a logic function circuit(31), a reversible logic function circuit(33), a compensation circuit(35) and a clamp circuit(37). The logic function circuit operates in a first clock from among power supply clocks having at least 8 phases during a cycle, calculates positive logic function of complementary dual rail using at least one NMOS transistor, and determines charge path for output nodes. The reversible logic function circuit operates in a second clock, calculates negative logic function of complementary dual rail, and determines charge path for output nodes. The compensation circuit compensates for swing reduction at an output node caused by a threshold voltage of NMOS transistors in the logic and reversible logic function circuits.
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