发明名称 VERIFICATION METHOD FOR ELECTRONIC CIRCUIT
摘要 PROBLEM TO BE SOLVED: To make verification work efficient and shorten development period of an LSI, by enabling verification of the power down action of an analog circuit to be performed surely without errors with simple operations, in a circuit where an analog circuit and a digital circuit are mixed. SOLUTION: A circuit diagram, where an analog circuit and a digital circuit are mixed, is inputted (S1), and from among the circuits, a digital block of which is the logic is to be verified is designated (S2). Input pattern for verification of the logic of the digital block is inputted (S3), and logical verification of the digital block is performed (S4) by the input pattern, and a logical verification file is created nd registered (S5) from the result. The analog block is indicated, and for this indication, each node of the analog block is indicated by colors, according to the logical condition, based on the result of logical verification, and at the same time, the analog block or the cell constituting this is indicated (S6) by colors, according to the operation state.
申请公布号 JP2000323575(A) 申请公布日期 2000.11.24
申请号 JP19990128943 申请日期 1999.05.10
申请人 ASAHI KASEI MICROSYSTEMS KK 发明人 NARITA MAKOTO;WATANABE TAKAHITO
分类号 H01L21/82;H01L21/66;(IPC1-7):H01L21/82 主分类号 H01L21/82
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