| 摘要 |
PROBLEM TO BE SOLVED: To reduce a step between a memory cell array region and a peripheral circuit region by a method wherein a cylindrical electrode contains a memory cell, a porous tube part is formed, and an insulating layer is formed only inside the peripheral circuit region in order to decrease the step by the cylindrical electrode. SOLUTION: A MOS transistor 10b which controls a memory cell is formed inside a peripheral circuit region. An interlayer insulating layer 14 is formed to cover the MOS transistor 10b. A wiring layer 15b is formed on the interlayer insulating layer 14. An interlayer insulating layer 16 is formed so as to cover the wiring layer 15b. In addition, an insulating layer 6 and an insulating layer 20, which are composed of a silicon oxide film used to relax a step by a cylindrical electrode 1 which is formed only in the peripheral circuit region and in which a porous tube part is formed, are laminated and formed on the interlayer insulating layer 16. As a result, a step between a memory cell region and the peripheral circuit region can be decreased. |
