发明名称 FRAME SYNCHRONIZATION METHOD AND FRAME SYNCHRONIZATION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To allow a user side to optionally set the number of backward protection stages and the umber of forward protection stages depending on purpose. SOLUTION: The frame synchronization circuit is provided with a frame synchronization pattern detection circuit 1 that detects a frame synchronization pattern from received frame data to provide an output of a frame synchronization pattern detection signal, a frame synchronization state transition management circuit 3 that manages a state transition of frame synchronization and a frame timing generating circuit 2 that detects transition of the management circuit 3 from the hunting state to generate an enable signal. The management circuit 3 manages the number of times of detection of the frame synchronization pattern and the number of times of noon-detection based on the enable signal and the frame synchronization pattern detection signal, transits the state from the hunting state into the synchronization establishing state when the frame synchronization patterns are consecutively detected for the number of the backward protection stages set optionally, and transits the state from the synchronization establishing state into the hunting state when the frame synchronization patterns are consecutively not detected for the number of the forward protection stages.</p>
申请公布号 JP2000324116(A) 申请公布日期 2000.11.24
申请号 JP19990126190 申请日期 1999.05.06
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 KAMEYAMA CHIHIRO
分类号 H04J3/00;H04J3/06;H04L7/08;H04L12/70;H04Q11/04;(IPC1-7):H04L12/28 主分类号 H04J3/00
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