DIGITAL PLL CIRCUIT

摘要

PROBLEM TO BE SOLVED: To obtain the digital PLL circuit which secures excellent reception characteristics by doubling the internal circuit plane of the digital PLL circuit and alternately processing burstlike data signals at a request to narrow down the burst intervals of burstlike data signals. SOLUTION: In the double-plane digital PLL circuit, received burstlike data signals which are different in phase and variation quantity of jitter and duty cycle distortion by bursts are distributed alternately to an internal circuit 0-plane 2 and an internal circuit 1-plane 3 to perform phase synchronizing operation and data discriminating operation. Processing time for the phase synchronizing operation and data discriminating operation for the burstlike data signals in the digital PLL circuit are normally needed, but the processes of the burstlike data signals may overlap with each other because of the two planes and a process wait state can be eliminated. Consequently, the intervals of the burstlike data signals can be made narrow without spoiling the reception characteristics.