Symbol timing recovery based on adjusted, phase-selected magnitude values

摘要

A digital communication receiver (10) includes a magnitude-based symbol synchronizer (38) which separates complex phase attributes from magnitude attributes. The phase attributes are processed by a phase processor (78) which identifies clock adjustment opportunities. The magnitude attributes are processed by a magnitude processor (76) that generates a phase error estimate signal (82), which in turn drives a clock generator (24) in a phase locked loop (54) to achieve symbol synchronization in a non-data-directed manner. An additional adjustment feedback loop (114, 128) includes a phase error offset generator (52) and operates in conjunction with the phase locked loop (54) to allow the phase locked loop (54) to achieve lock and a robust operating point in spite of distortion in a received input analog signal (12).