| 摘要 |
A heterogeneous programmable gate array (100) has an unstructured logic sub-array (102) and a structured logic sub-array (104). An unstructured input/output interconnect structure (106) delivers unstructured-to-unstructured input/output signals to the unstructured logic sub-array, while a bussed input/output interconnect structure (108) delivers structured-to-structured input/output singals to the structured logic sub-array. A control signal bus (110) is connected between the unstructured logic sub-array and the structured logic sub-array to deliver unstructured source signals therebetween. A bussed signal bus (112) is connected between the unstructured logic sub-array and the structured logic sub-array and the structured logic bus-array to deliver structured source signals therebetween.
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