| 摘要 |
A monolithic CMOS programmable digital intermediate frequency receiver (20) includes a programmable memory (29), a clock generator (26), a sigma delta converter (22), a digital downconverter (24), and a decimation filter network (28). The programmable memory (29) receives and stores a first value representative of a programmable parameter k and a second value representative of programmable parameter N. Coupled to the programmable memory (29), the clock generator (26) generates a first clock signal, a second clock signal and a third clock signal. The first clock signal has a first frequency, f1, the second clock signal has a second frequency approximately equal to f1/k and the third clock signal has a third frequency approximately equal to f1/N. The sigma delta converter (22), the digital downconverter (24) and the decimation filter network (28) use the respective first, second and third clock signals to generate the respective set of digital signals.
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