Packaged surface mount (SMT) chips having matched top contacts and bottom contacts are stacked. Chip features are selected to provide the desired connectivity between chip layers with a greater ease of manufacture. In one embodiment, additional spacing and routing layers are optionally provided between layers. In another, chips are differentiated by optionally providing different conductor and/or nonvolatile cell configurations. In yet another, a minority of a substrate's contacts are configured for aligning with a dielectric region of a spacing layer or substrate to create very low capacitance signal paths between stacked chips.
申请公布号
WO0068996(A1)
申请公布日期
2000.11.16
申请号
WO1999US25015
申请日期
1999.10.26
申请人
SEAGATE TECHNOLOGY LLC
发明人
CHAU, CHIN, LOW;WOO, OSCAR;FABRY, MICHAEL, R.;JUNGE, TERRY, A.;TIANG, FEE, YIN;CHOON, AN, AW;OLSON, JONATHAN, E.