发明名称 Hochauflösende Verzögerungsschaltung
摘要 A delay circuit is to produce a delay timing which is larger than one cycle time of a reference clock while the resolution of which is smaller than the one cycle time of the reference clock. The delay circuit includes a coarse delay circuit for producing a borrow signal having a delay time which is an integer multiple of one cycle time of a clock signal supplied thereto, a divider for dividing the frequency of the reference clock to produce the clock signal, a flip-flop circuit for delaying an incoming signal by one cycle time of the reference clock, a re-timing circuit for receiving an output signal from the flip-flop circuit and producing a coarse delay signal in synchronism with the reference clock, a decoder for receiving the borrow signal from the coarse delay circuit and selectively providing the borrow signal to either the flip-flop circuit or the re-timing circuit, and a fine delay circuit for adding a fine delay time which is smaller than the one cycle time of the reference clock to a coarse delay signal from the re-timing circuit.
申请公布号 DE19811868(C2) 申请公布日期 2000.11.16
申请号 DE1998111868 申请日期 1998.03.18
申请人 ADVANTEST CORP., TOKIO/TOKYO 发明人 SATO, MASATOSHI
分类号 G01R31/317;G01R31/319;H03K5/135;(IPC1-7):H03K3/86;H03K5/159 主分类号 G01R31/317
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