| 摘要 |
PURPOSE: A delay synchronization circuit is provided, which additionally includes a digital delay and oscillation means capable of generating a high frequency signal to generate a signal having various phase delays, thereby overcoming operation range limit. CONSTITUTION: A delay synchronization circuit includes a phase detector(400) for detecting the phase of an external clock signal, a controller(410) for receiving the output signal of the phase detector to control the state of reset and control signals, and a first delay(420) for transmitting the external clock signal, having a predetermined delay time. There is also included first and second oscillators(430,440) for generating high frequency signals, a second delay(450) for receiving the delayed clock signal sent through the first delay to generate a plurality of clock signals having different phase delays under the control of the output signal of the first oscillator and the reset signal, a third delay(460) for receiving the delayed clock signal transmitted through the first delay to generate a plurality of clock signals having different phase delays under the control of the output signal of the second oscillator and the reset signal, a selector(470) for selecting a pair of clock signals having the same phase delay, and a logic means(480) for combining the pair of clock signals selected by the selector to generate an inner reference clock signal having the same period as that of the external clock signal.
|
