| 摘要 |
PURPOSE: A write control driving circuit is provided to reject a pulse of combined address transition detect signal which delays write operation, in order to transmit data accurately in high speed chips. CONSTITUTION: The write control driving circuit includes the first logic circuit(DE1) and the second logic circuit(DE2). The first logic circuit receives the first pulse of the combined address transition detect(ATDS) signal generated at the application point of a write enable signal and the second pulse of the combined address transition detect signal and outputs a delay control signal(FATDS) which rejects the first pulse only. The second logic circuit receives a coding signal(WEZ) which is generated by combining the write enable signal(WE) and the output of a decoder, the delay control signal(FATDS) and the coding signal(WEZ) to output a write control signal(WC). The coding signal is generated by logically combining the write enable signal(WE) and the output of the Z-decoder by way of a NAND gate.
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