| 摘要 |
<p>PURPOSE: A delay circuit is provided to be capable of maintaining a constant delay time regardless of the variance of source voltage by differently applying predetermined voltage to the substrates of an NMOS transistor of an inverter and an NMOS transistor of a capacitor, respectively to apply different threshold voltages the substrates. CONSTITUTION: The delay circuit includes a plurality of inverters(INV1-INVn), and a plurality of NMOS transistors(NMC1-NMCn-1) each of the gates of which is connected to a corresponding one of the output terminals of the inverters, and the drains and sources are commonly connected with a ground voltage(VSS), respectively, wherein a capacitance substrate voltage(VBBI) is applied to a substrate. Here, the gates of the inverters are commonly connected for thus forming an input terminal, and the drains of the same are commonly connected for thus forming an output terminal. In addition, in each of the inverters, PMOS transistors(PMI1-PMIn), the sources of which are connected with the substrate, respectively, and NMOS transistors(NMI1-NMIn) in which the inverter substrate voltage(VBBI) is connected with the substrate are connected in series between the externally applied voltage(VCC) and the ground voltage(VSS).</p> |
